what can I do to delay the source

TimeQuest can help data delays (not clk delay) anywhere within one clock period of 160MHz at least but its control is not fine and may jump coarsley as you change parameters.

This is the very mechanism of getting input io timing when you use set_input_delay.

Try experimenting as follows:

tell TQ your ddr clk speed of 165 and that data is edge aligned i.e. tCO = 0 so set input delays to zero. Make sure you select io register (fast io) and compile then run TQ and check the datasheet section which tells you figures for setup/hold at FPGA boundary (pins).

In effect the timing window which is about .6 ns around clk edge (internally at register) should be moved away from clock edge at pins.

e.g. you might see tSU = 2 n and tH = - 1.4ns indicating a delay of about 2ns has been applied to data.

If your figure are different then play with delay figures.

At the same time TQ will tell you about timing violations in the section called io timing