what can I do to delay the source

A PLL solution may be too involved. io delay is not that fine...

One practical option is to look at optimum delay point for all frequencies.

Remember, data does not need to be centre aligned per se. What matters is no timing violation at FPGA io registers.

My own measurement of stratix 4 io timing window is that it is very small e.g. 0.6ns.

Your worst frequency has period of 6 ns and slowest one is 40 ns.

so if you push the data towards 1.5 ~ 2 ns from clk egde then it might be ok for all cases I believe. In the case of 40 ns period for example this location will not violate either edge.

The trick is to get 1.5 ~ 2 ns strictly under control and TimeQuest should confirm these figures.