what can I do to delay the source

The delay chains are not nearly as good as a PLL, because the they are not compensated over PVT. An 800ps delay in the slow corner might only be a 400ps delay in the fast corner. That's why a PLL will allow much higher rates.

That being said, you're not running at super fast rates, and hence it might be possible. But you'll never know without timing constraints. I would put those in first. Doing paper analysis of delay chains and what not is generally too hard, because paper analysis doesn't cover PVT/ODV, etc.

Note that your data drives directly to the registers, while the clock has a long way to go, hence it will be the longer delay. That's why same edge capture is so useful. If you don't do that, then the clock delay may be 3ns, and the data delay will have to be more than 3ns, and you'll never meet timing over PVT. With same edge capture, you want your data delays to be shorter than the clock, which is do-able.

Again, I would put the constraints in first thing and analyze what they're doing. Once they're correct, start playing with the clock tree. Put it on a global. If that doesn't work, try a regional. If that doesn't work try local routing.