Honored Contributor
Honored Contributor165Mhz DDR might be do-able without a PLL, it's just tight. Depends on device and what-not. Note that if you can do that, then the lower rates should just work, as the edges move out. You'll want to add a multicycle to make sure you're doing "same-edge" capture. Assuming they come in edge-aligned:
create_clock -period 6.060 -name fpga_clk [get_ports fpga_clk] create_clock -period 6.060 -name ext_clk derive_clock_uncertainty set_input_delay -clock ext_clk -max 0.5 [get_ports {data[*]}] set_input_delay -clock ext_clk -min -0.5 [get_ports {data[*]}] set_input_delay -clock ext_clk -max 0.5 [get_ports {data[*]}] -clock_fall -add_delay set_input_delay -clock ext_clk -min -0.5 [get_ports {data[*]}] -clock_fall -add_delay set_multicycle_path -setup 0 -rise_from ext_clk -rise_to fpga_clk set_multicycle_path -setup 0 -fall_from ext_clk -fall_to fpga_clk The multicycles are the most confusing part, but they basically go for same edge latching. This is good since the clock tree will be longer than the datapath, and hence will buy you some setup margin.
