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Isn't the ALTLVDS_Rx megafunction a dedicated DESER circuit in Cyclone?
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No, not in Cyclone.
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So the LVDS receiver will automatically adjust the receiver phase for maximum RSKM if use a PLL?
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Only on families that support DPA (Stratix II-IV, Arria I-II). Not in Cyclone I-IV and other families.
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In Xilinx design, the SERDES frame and bit clock go through a DCM (Digital Clock Manager) to align receiver phase, it is not used directly.
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In Altera you have two options
a) use the frame and bit clock directly.
You won't be be able to have any control over phase, so it's not very recommendable.
b) generate the bit clock from the frame clock using a PLL.
In a device that supports DPA, the altlvds_rx function will be able to automatically adjust the bit clock's phase to maximize RSKM.
On the ones that don't support DPA, it won't. But in PCB, where delays are more or less stable, you can manually tune the PLL's output phase to get a good RSKM.
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