What are the differences between Altera & Xilinx Deserialization?

So the LVDS receiver will automatically adjust the receiver phase for maximum RSKM if use a PLL?

Isn't the ALTLVDS_Rx megafunction a dedicated DESER circuit in Cyclone?

In Xilinx design, the SERDES frame and bit clock go through a DCM (http://www.google.com.hk/url?q=http://www.xilinx.com/support/documentation/ip_documentation/dcm_module.pdf&sa=x&ei=jffhs-vghc-tkaxxwrm9cq&ved=0cagqzgqoadaa&usg=afqjcnhi23tc7buynxnz1e16-128gobl3g)(Digital Clock Manager) to align receiver phase, it is not used directly.

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If you use a PLL for the LVDS reveiver, the bit clock (fast clock) is generated from the FCO by frequency multiplication automaticly. You don't have an option to use a different bit clock in this case.

With Cyclone family, that has no dedicated DESER circuit, you're basically able to save the receiver PLL and supply SERDES frame and bit clock from the ADC. But you loose the option to adjust the receiver phase for maximum RSKM (receiver input skew margin). I didn't yet try this design variant, it may be necessary for a Cyclone design that runs short of PLLs.

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