What are the differences between Altera & Xilinx Deserialization?

Only one clock is necessary, as PLL does the rest. Technically you should be able to do everythign with the altlvds block. I don't know enough about the bit swap mux, but would be surprised if it were necessary. The data should come out in parallel to your data clock rate. If the order is incorrect, you just switch the hookup. I'm not sure what they're changing on the fly.