What are the differences between Altera & Xilinx Deserialization?

I don't need very high speed, I need to deserialize ADC converstion from Texas Instruments ADCs. Most of them are 40MSPS*14bits.

What puzzles me mostly are the details. For example, ALTLVDS RX seems only need one input clock (AD clock), it generate bit clock using PLL, while Xilinx design uses two input clocks, need AD clock and bit clock from the ADC chip.

Xilinx design need "Bit Swap Multiplexer" and a lot of components,

but Altera design seems only need ALTLVDS_RX. Does Altera design need those components?