What Altera tool can we use to manually place and route, especially LUT locations

If the timing constraints are correct, accurate, and detailed, failing paths should not be spread all over the chip. There are always reasons why the Fitter does what it does, and going back to the design and timing constraints and correlating with timing reports is your first best step. Now, isolating critical logic from non-critical logic with LL can certainly help after this, but an initial compile without LL can be used to help you understand what the Fitter is doing and decide if LL is really necessary.