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I would argue that even using LL regions may not be preferred. Without LL regions, the Fitter can use any resources in the device and select the best ones based on the design and the timing constraints. Floorplanning with LL limits what the Fitter can choose. The grouping you mentioned is not really required by the modern Fitter. It was an issue in the past, though. Accurate timing constraints are essential.
Some design flows, though, absolutely require LL, such as partial reconfiguration and periphery design block reuse.
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Q15 is hardly in the past. Ive needed LL regions to make a design using 90% logic. Without locking down specific entities, it would just spread them out and fail timing. locking them pretty much guaranteed timing.
And then another design (Q10 mind you) had 15 regions because it had 90% ram and 90% dsp usage. If you didnt lock down the regions, again, it just died a miserable death. Even then, it needed 10 seeds to get 1 good one. But it didnt help that one clock was running at 350+Mhz. This strategy was recommended by Altera!
Leaving it to the fitter is all fine until you consistantly fail timing, and your failing paths are spread all over the chip.
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