What Altera tool can we use to manually place and route, especially LUT locations

@sstrell the grouping issue is very definitely not a thing of the past at all. We have a design which is split into 12 DSP processing cores which each take a fraction of incoming data from a bus, process it, and then remerge at the end. When left to its own devices the fitter is either unable to fit the design, or it fails timing miserably. By grouping each core into its own LL region, the design fits well (~60% resource usage) and meets timing with ease - removing ~5ns of negative slack in the process (which is a lot at 200MHz). Similar story on another design with multiple cores.