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If you want to constrain logic to a particular area of a chip, that is what LogicLock regions are for as sstrell mentions.
With LL regions you basically define a region of the chip in and then assign portions of the design such as partitions or specific registers/LUTs/DSP blocks/RAMs etc. You can then specify what you wish to be constrained within the block - for example you might assign a partition but only want M20Ks or DSP blocks to be constrained, so you could exclude things like LUTs or routing.
LL regions have a distinct advantage over assigning specific LUTs to specific regions in that it still allows the fitting tools to use their very good optimisation abilities to decide where bits should go whilst solving the issue of the fitter not being able to see the forest for the trees. If you have lots of chunks of the design with interconnections, the fitter can get confused and struggle to optimise what should be where. By constraining these chunks into regions it helps the fitter see what bits should be grouped and so start optimising those groups internally more strongly as it knows you want them to be packed.
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I would argue that even using LL regions may not be preferred. Without LL regions, the Fitter can use any resources in the device and select the best ones based on the design and the timing constraints. Floorplanning with LL limits what the Fitter can choose. The grouping you mentioned is not really required by the modern Fitter. It was an issue in the past, though. Accurate timing constraints are essential.
Some design flows, though, absolutely require LL, such as partial reconfiguration and periphery design block reuse.
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