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Where did the code come from? Did you write it?
It looks very much like code for a test bench to me and not something intended for synthesis. The code contains a relatively large number of 'always @' statements. Between them the are implying a lot of signals that will be interpreted as clocks, something that'll cause Quartus a lot of trouble when trying to fit it to the small CPLD you're using.
The following discusses always blocks and their intended use:
verilog: always @ blocks (
http://www-inst.eecs.berkeley.edu/~cs150/sp13/resources/always.pdf)
I suggest you have a good look through it. I hope it helps.
Regards,
Alex
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Hi, thanks for the response. I thought I'd already responded to this thread, but I cant see my post. The code is an Altera sample.
I've since re-written the code myself and its running much better, except for one thing -- the clock divider.
I'm generating my SPI clock from a counter and using a bit index to perform a power of 2 divide for the clock. The clock generation looks like this --
reg rControl;
wire rClkDivide = rControl;
...
always @ (posedge iclkHost)
begin
...
rClockCounter <= rClockCounter + 1;
rSPIClk <= rClockCounter;
...
end
But I find when I use this, I get random errors occurring in the data with missed byte reads. But if I use a fixed clock like this --
always @ (posedge iclkHost)
begin
...
rClockCounter <= rClockCounter + 1;
rSPIClk <= rClockCounter;
...
end
It works perfectly, and that's at a full 7.5Mhz. At any clock divider taken from the control register, I get errors. I'm really not sure why??
Any pointers on this much appreciated, as otherwise my SPI code is working really well.
Thanks!
Honored Contributor
