Weird sticky bit in SPI data

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Where did the code come from? Did you write it?

It looks very much like code for a test bench to me and not something intended for synthesis. The code contains a relatively large number of 'always @' statements. Between them the are implying a lot of signals that will be interpreted as clocks, something that'll cause Quartus a lot of trouble when trying to fit it to the small CPLD you're using.

The following discusses always blocks and their intended use:

verilog: always @ blocks (http://www-inst.eecs.berkeley.edu/~cs150/sp13/resources/always.pdf)

I suggest you have a good look through it. I hope it helps.

Regards,

Alex

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This is Altera sample code from here (search for SPI Master) --

http://www.altera.co.uk/support/examples/max/exm-max.html

Thanks for the feedback, I think I'll rewrite it myself now I understand better how SPI works. I must admit, it's not how I would have written it, but then I'm new to hardware design, so I usually think its my lack of experience as to why I don't understand the approach.