Weird sticky bit in SPI data

Where did the code come from? Did you write it?

It looks very much like code for a test bench to me and not something intended for synthesis. The code contains a relatively large number of 'always @' statements. Between them the are implying a lot of signals that will be interpreted as clocks, something that'll cause Quartus a lot of trouble when trying to fit it to the small CPLD you're using.

The following discusses always blocks and their intended use:

verilog: always @ blocks (http://www-inst.eecs.berkeley.edu/~cs150/sp13/resources/always.pdf)

I suggest you have a good look through it. I hope it helps.

Regards,

Alex