Honored ContributorBeen looking through the documentation but haven't found my answer yet...
how exactly does waitrequest work? How does the Avalon bus control it? I'm only asking because my custom component is trying to do a pipeline read of SDRAM but I am waiting many clock cycles (640ns) between reads because the waitrequest signal is still asserted. What am I overlooking here? 640ns is way too long.
Honored Contributorwait_request is asserted by the slave, or by adapter logic created by the sopc system and attached to the slave, when the bus can not accept any more transactions. look at what the maximum number of pending transfers is for both the master and the slave, and that will most likely correspond with when the waitrequest is asserted.
Note that SDRAM has a variable read_request to read_valid length, and 640ns doesn't seem that high depending if that row is already open or not. However, when you pipeline it and have multiple requests posted at the same time it hides some of that latency.
