Honored Contributor
Honored Contributorthis could happen from bad verilog coding?
as far as i know digital output can't be biased. its output only logic levels 0v and Vdd. on the board there is nothing connected between the HW pin and the scope probe. in addition, if i probing other HW pins that wired with the same digital signal (1MHz clock) i see the expected clock on the scope screen, rail to rail. the print screen of the signal from the biased HW pin is attached. so my conclusion is my test setup from the probe perspective is ok. which else configuration parameters in the quartus project should i check?
