Altera_ForumHonored Contributor11 years agovip_top for video example design Hello all, I want to to use the eample design video donné par altera but I can't find the .bdf file that contains the graphic modules. I f someone have this example please I need it. Cordi...Show More
Altera_ForumHonored Contributor11 years agothere should be a top.v or top.vhd file which connect the QSYS-System to the PINs.
Recent DiscussionsVcm for the clock input pins of agilex5 E-series FPGA A5ED065BB32AE5SR0carry chain tdcDoes the Post-Configuration BSDL Generator for Cyclone 10 LP require an NDA?EMIF Pin Assignment for Agilex 7 FPGA I-Series DevKit (DK-DEV-AGI027R1BES)Timing Slacks inside Altera IP