Honored Contributor
Honored ContributorHi Jakob,
Thanks for the reply. 1 - Your pixel clock may not be high enough for the VIP components. You need to allow for delays within the blocks of a few clock cycles plus the overhead of the video control packets. The vip blocks are clocked at the pixel rate of the incoming video; approx 110MHz, but as there is no blanking/sync information in the Avalon packets I figure they should have an efficiency improvement, requiring a 10% to 20% lower clock. I have successfully run the video path at 100MHz before from a static clock source. What do you think is the fastest I can clock the video path? My device is EP3C16F484C8N. The Altera docs seem pretty vague on this front. 2 - How much line buffering is in your CVI and CVO blocks? I'm buffering 2048 pixels on the CVI, and 512 pixels on the output. I have experimented with many different values and this combination work (when no control ports are enabled.) I'll triple this buffering for the sake on investigation. 3 - How wide is your DDR2 interface and how fast is it running? The DDR2 is running full rate, 150MHz, with a 16 bit physical, 32 bit effective interface. As above, bandwidth does not appear to be an issue when the control ports are disabled. I will up this rate to 167MHz for the sake of investigation. I'll post code tomorrow when I'm at work, but it is very simple IOWR(x_BASE, 0x01, 0x01) type stuff. I'll drop some screen shots of my sopc build and frame buffer settings, etc, too. Thanks for all your help, I really appreciate the time (I'm sure everyone else does too) that you spend helping newbies like me! Regards, Brent.
