Honored Contributor
Honored ContributorLet me first say that so far most of the time people have trouble with the VIP suite it's due to how the overall video system is put together rather than how the individual blocks are being used. Usually the biggest problems people have are with choosing the right clock frequency for the VIP blocks, and buffering.
1 - Your pixel clock may not be high enough for the VIP components. You need to allow for delays within the blocks of a few clock cycles plus the overhead of the video control packets. 2 - How much line buffering is in your CVI and CVO blocks? 3 - How wide is your DDR2 interface and how fast is it running? With regards to the odd register reads, can you post a bit of your C code so we can see how you're accessing the components? Also note, if the DDR2 is behind the pipeline bridge, it's real address range with relationship to anything in front of the bridge is 0x0200_0000 to 0x03ff_ffff. If the DDR2 and VIP blocks were really overlapping that would definitely not be okay but SoPC builder "shouldn't" allow you to do that. Jake
