VHDL VERILOG Pin Planner and Quartus II -- case sensitivity trouble --

Step 2, after too much struggle about no idea what can be wrong, included here as attachment are two images of pin planner one from VHDL top and one from Verilog, I cannot see differences nor I am able to grasp what is different from top level module interface seems quite similar and signals are assigned same manner.

Original Verilog

assign mdio_in = NET_MDIO;

assign NET_MDIO = mdio_oen == 0 ? mdio_out : 1'bz;

Translated VHDL:

mdio_in <= NET_MDIO;

NET_MDIO <=

mdio_out when mdio_oen = '0'

else 'Z';

One thing left me astonished is that an output signal got assigned to a value from verilog, VHDL report error and I agree.

Verilog assign a value to output:

.tse_mac_status_connection_ena_10 ( 1'b1 ),

VHDL report error

tse_mac_status_connection_ena_10 => '1' , -- : out std_logic