VHDL timing

--- Quote Start ---

Let's say that I am not simulating the design but burning it to an actual CPLD. Isn't there a race condition between the enable and input signals?

--- Quote End ---

That would depend on the characteristics of the PLD and the routing / logic delays for your particular layout. You could potentially get a glitch on the output - it depends what the on/off and propagation delays are for the buffer and which signal arrives first.

You could always run a gate level simulation with timing delays to check this - but it could change for each compilation.

If it's really an issue then you might want to think about your design in a bit more detail.

--- Quote Start ---

Can I always assume that the buffer's output will change immediately?

--- Quote End ---

The output will never change immediately on an actual chip - there will always be some delay there - you need to work out how much is OK for your design.

Depending on what device you're using you could add timing constraints so that you don't end up with a glitch at the output.

have a think about what the signals are actually doing when they get to the outside world and whether you have a problem or not before diving into constraints or changing your design.