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Altera_Forum's avatar
Altera_Forum
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17 years ago

VHDL timing

Hi all, I am new to VHDL so I suppose that my question is pretty basic: Suppose I have a simple buffer with input, output and enable. The input is connected to the output if enable = '1'. When ...
Altera_Forum's avatar
Altera_Forum
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17 years ago

@ batfink: Thanks for the detailed answer.

Let's say that I am not simulating the design but burning it to an actual CPLD. Isn't there a race condition between the enable and input signals?

Can I always assume that the buffer's output will change immediately?