VHDL timer

Ok this is what I wrote in VHDL and when I run the code (in quartus II) I got success put when I go to the RTL viewer to draw the circuit I gut only the pin for input and output but when I do the same for AHDL code I have very big and different circuit.

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity two is

Port (

clk : in std_logic;

enl : in std_logic;

second : out std_logic

);

end two;

architecture Timer of two is

constant count : natural := 48000000;

-- I used 24MHz clock

begin

process (clk, enl)

variable count : natural range 0 to count;

begin

if (enl ='1') then

if (count = 48000000) then

count := 0 ;

second <= '1';

else

count := count+1;

second <= '0';

end if ;

second <= '0';

end if ;

end process;

end Timer;