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Altera_Forum's avatar
Altera_Forum
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13 years ago

VHDL testbanch

Hi, I described clock divider from 50MHz to 1Hz. I also wrote testbanch, unfortunately it takes too much time to run 1 cycle at 1Hz. How can I make the simulation faster? Th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

--- Quote Start ---

Hi,

I described clock divider from 50MHz to 1Hz.

I also wrote testbanch, unfortunately it takes too much time to run 1 cycle at 1Hz.

How can I make the simulation faster?

Thanks

--- Quote End ---

scale down your division for say 50K for simulation only