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Altera_Forum's avatar
Altera_Forum
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12 years ago

VHDL testbanch

Hi, I described clock divider from 50MHz to 1Hz. I also wrote testbanch, unfortunately it takes too much time to run 1 cycle at 1Hz. How can I make the simulation faster? Th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

you probably cant. Just wait.

Its probably slow for 2 reasons:

1. You have a cheap version of modelsim (cheaper versions run slower)

2. Your code is unnecessarily complicated (more code slows the simulation down).

So, assumiung you have no control over 1. the only option is to fix 2.

How about trying a clock enable instead? logic clock dividers are not recommended.