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Honored Contributor
Honored Contributorvhdl syntax error
hello, here is part of my vhdl codes. ce : in std_logic; addr : in std_logic_vector (15 downto 0); process(ce, addr) variable gpio_enable : std_logic ; begin case ce and ...
Altera_ForumHonored Contributor
Honored Contributorce : in std_logic;
addr : in std_logic_vector (15 downto 0); ----------------------------------------------------- gpio_enable <= '1' when (ce='1' and addr(7 downto 5)="001" ) else '0'; -----------------------------------------
