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Altera_Forum
Honored Contributor
Honored Contributorvhdl syntax error
hello, here is part of my vhdl codes. ce : in std_logic; addr : in std_logic_vector (15 downto 0); process(ce, addr) variable gpio_enable : std_logic ; begin case ce and ...
Altera_ForumHonored Contributor
Honored ContributorHi,
I believe you want to concatenate rather than "and". Try this signal sub_addr : std_logic_vector(3 downto 0); -- sub_addr <= ce & addr(7 downto 5); case sub_addr is when "1001" => you might as well just use a single combinatorial assignment Kaz
