Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

vhdl syntax error

hello, here is part of my vhdl codes. ce : in std_logic; addr : in std_logic_vector (15 downto 0); process(ce, addr) variable gpio_enable : std_logic ; begin case ce and ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Hi,

I believe you want to concatenate rather than "and". Try this

signal sub_addr : std_logic_vector(3 downto 0);

--

sub_addr <= ce & addr(7 downto 5);

case sub_addr is

when "1001" =>

you might as well just use a single combinatorial assignment

Kaz