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You can create a std_logic_vector of zeros using "others" that's nice.
constant bus_width : integer := 32;
signal my_signal : std_logic_vector(bus_width -1 downto 0);
constant zeros : std_logic_vector(bus_width -1 downto 0);
zeros <= (others => '0');
...
if (my_signal = zeros) then...
This makes it a little cleaner.
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You cannot "assign" a constant, you can only initilise it at declaration.
For the origional poster - Im on the opinion that its always best to write explicitly what you mean. So if you are checking that all bits in the bus are zero, then use the and_reduce, or when VHDL 2008 gets support, you can just write the following:
if (and my_slv) then
....
But if your std_logic_vector represents a number, compare it to the integer 0.
if my_slv = std_logic_vector( to_unsigned(0, my_slv'length) ) then
...
Now I know you said you didnt want to have type conversion functions, but this way shows to another engineer that your std_logic_vector represents an integer and not just a collection of bits. This would beg another question though - why are you using std_logic_vectors to represent integers?
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