VHDL starter/biginer

hello everyone i new in using modelsim xe iii/starter and have this project to start:

1. Write a VHDL description of an SR latch

a. Use the characteristic equation

b. Use logic gates

c. Use a conditional assignment statement

2. A 4-bit magnitude comparator chip (http://focus.ti.com/lit/ds/symlink/sn74ls85.pdf) compares two 4-bit numbers and produces a three bit output.

a. Write behavioral VHDL description for this comparator chip.

b. Using structural VHDL, cascade two 4-bit chips to make an 8-bit magnitude comparator. Include block diagram.

3. The 74194 four-bit bidirectional shift register (http://focus.ti.com/lit/ds/symlink/cd74hc194.pdf) includes an asynchronous reset, parallel load and left/right shift.

a. Write a behavioral VHDL model for the 74194.

b. How can this be extended to an 8-bit shift register? Implement in VHDL.

4. Design a counter that repeatedly counts in the sequence: 0000, 0001, 0010, 0100, 1000, 0000, …. An asynchronous load input loads the counter with 0000.

i need help for this project while in the mid-time i'm reading and getting familiar with the program...any help will be truly appreciated...