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Altera_Forum
Honored Contributor
Honored ContributorVHDL Protected type help
Hi everyone,.. I'm new in VHDL and FPGA, sorry for my lame question. Here I have a project, and I thing I will need to use shared variable, here is the code I made : --- Quote Star...
Altera_ForumHonored Contributor
Honored ContributorTricky and amilcar =>
--- Quote Start --- The basic guide is - dont use shared variables. --- Quote End --- --- Quote Start --- Yeap, do not use shared variables. Sometimes, they just do not work. --- Quote End --- Okay, shared variable should be avoided, thanks for your advice... Mr. FvM => Your solution seem good, okay let me think and try it... Thanks for your help... :) I appreciate that... :)
