VHDL Protected type help

To see, if the 6 MHz clock is toggling, you can use synchronous edge detection. It's easy in this case, because every high or low state of clk6 will be sampled at least once due to the frequency ratio.

signal clk6_s : std_logic;
signal clk6_v : std_logic;
signal edge_cnt: integer range 0 to 3; 
process (clk24)
begin
if rising_edge(clk24) then
  clk6_s <= clk6;
  clk6_v <= clk6_s;
  if (clk6_s XOR clk6_v) = '1' then
    -- clock edge detected
    edge_cnt <= 3;
  elsif edge_cnt > 0 then
    edge_cnt <= edge_cnt - 1;
    if edge_cnt = 1 then
      -- clock just stopped
    end if;
  end if;
end if;
end process;