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Altera_Forum
Honored Contributor
16 years agoVHDL Protected type help
Hi everyone,.. I'm new in VHDL and FPGA, sorry for my lame question. Here I have a project, and I thing I will need to use shared variable, here is the code I made : --- Quote Star...
Altera_Forum
Honored Contributor
16 years ago --- Quote Start --- From what I read from The Designer Guide to VHDL 3rd Edition book, page 589, on the top page, it said that shared variable must be of protected types... how about that? --- Quote End --- This is true, but because it would break a lot of VHDL'93 code (because VHDL 93 allows shared variables the way I showed you) mode compilers just throw a warning rather than an error by default and let you do it (you can change all the pedant settings if you want so it throws an error). The basic guide is - dont use shared variables.