Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

VHDL problem: inputs and constants

Hi all, I've a problem in VHDL. This code runs correctly: library IEEE; use IEEE.std_logic_1164.all; entity CLOCK_SIM is generic ( constant FREQ : integer:=10000000; constant DUTY ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Hi TRicky,

thanks to your help I solved the problem.

Here's the simple code: 


library IEEE;
use IEEE.std_logic_1164.all;
entity pwm_DC is
 port
 (
  f      : in real;
  d      : in real;
  output : out STD_LOGIC
 );
end pwm_DC;
architecture pwm_DC_arch of pwm_DC is
begin  
 -- Processo principale: generazione Duty Cycle
 MainProcess : process
  variable FREQ  : real;
  variable DUTY  : real;
  variable RDUTY : real;
  variable TCLKH : time;
  variable TCLKL : time;
 begin   
   FREQ  := f;
   DUTY  := d;
   RDUTY := DUTY/100.0;
   TCLKH := 1 sec*((1.0/FREQ)*RDUTY);
   TCLKL := 1 sec*((1.0/FREQ)*(1.0-RDUTY));
   output<='1';
   wait for TCLKH;
   output<='0';
   wait for TCLKL;
 end process MainProcess;
end pwm_DC_arch;