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Altera_Forum
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14 years ago

VHDL problem: inputs and constants

Hi all, I've a problem in VHDL. This code runs correctly: library IEEE; use IEEE.std_logic_1164.all; entity CLOCK_SIM is generic ( constant FREQ : integer:=10000000; constant DUTY ...
Altera_Forum's avatar
Altera_Forum
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14 years ago

change TCLKH and TCLKL to signals or variables, and calculate their value at runtime, rather than at elaboration time. Currently, they use the initial value of FREQ, which will be -2^31.