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Altera_Forum
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14 years ago

VHDL problem: inputs and constants

Hi all, I've a problem in VHDL. This code runs correctly: library IEEE; use IEEE.std_logic_1164.all; entity CLOCK_SIM is generic ( constant FREQ : integer:=10000000; constant DUTY ...
Altera_Forum's avatar
Altera_Forum
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14 years ago

Hi Kevin,

thanks a lot for your help.

I just don't know how to do this.

I have to change the 2 constants

constant FREQ

constant DUTY

into two input signals.

By these 2 signals, I can calculate these 2 values

TCLKH

TCLKL

which I use to generate the output signal, a square wave with a duty cycle that depends on my two input values.

Can you help me?