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Altera_Forum
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14 years ago

VHDL problem: inputs and constants

Hi all, I've a problem in VHDL. This code runs correctly: library IEEE; use IEEE.std_logic_1164.all; entity CLOCK_SIM is generic ( constant FREQ : integer:=10000000; constant DUTY ...
Altera_Forum's avatar
Altera_Forum
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14 years ago

You have two constants (tclkh and tclkl) that will depend on the value of a signal 'freq' which in turn depends on the value of another signal 'f'.

Fix that up by changing those two constants to signals and give it another go...a calculated constant can't depend on a signal, since a signal is not 'constant'

Kevin Jennings