VHDL Noob question- Recursion?

Hello,

1) these two signals assignments are in different architectures. The E signal in one architecture is completely unbound from the same thing with the same name in another architecture; even if the two architectures are of the same entity. I might have missed the point.

Anyway, you can have a signal that is produced inside the a combinational function that feeds back in the same function. This may give you problems in simulation (if there is not a stable result this may give you too much oscillations and exhaust the number of delta for each signal transition), may give warnings in synthesis (I am not sure, I usually avoid things like this).

2) I think that you made some confusion about architectures, entities, instances. An architectures gives an incarnation of an entity. You can instantiate as many components as you need and theoretically as many instances as you need for a component. Any VHDL book and tutorials explains the chance to bond different instances of a component to different architectures in the same design. If you manage to do this (I had problems with this when I used Xilinx tools so I lost this habit and never used it with Altera ones), your different architectures will be threated independently. I suggest you to think at the instances of a component (even if you call different architectures for each) like threads with different memory spaces.

I hope this helps you. Sometimes VHDL can seem very strange and difficult, especially when the learner comes from a long experience of C, C++, Matlab and other languages that do not describe hardware. I think this is common to historical hardware description languages.

Regards,

Gabriele