Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorVHDL Help
Please help me to generate a clock in VHDL synchronised with rising edges of two external clocks.
External clocks are: 100Mhz and 124 Hz Clock to be generated: 10MHz The 10MHz clock is to be generated using 100MHz clock startin g from rising edge of 124Hz clock.22 Replies
Altera_Forumbut 124Hz clock is already there from an external source...i think i didn't get you
- Altera_Forum
Yes. But the code you have just samples the 10Mhz clock, it doesnt synchronise it. So the output clock will not be 10MHz, it will be, at most, 62Hz.
