VHDL For Altera De2 board normal text on LCD 16 x 2 help!!

I need help on displaying the "HITACHI " word on the altera DE2 lcd. the following is my codes.

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.all;

USE IEEE.STD_LOGIC_ARITH.all;

USE IEEE.STD_LOGIC_UNSIGNED.all;

entity hitachi is

port

(

reset,clk : in std_logic;

rs,rw,e,pwr,bkpwr : out std_logic;

data : out std_logic_vector(7 downto 0)

);

end hitachi;

architecture behv of hitachi is

type state_type is (wt,wt1,wt2,funcset,displayon,displayoff,displayclr,

entry,wrt,wrt1,wrt2,wrt3,wrt4,wrt5,wrt6,wrt7,entry1,wrt8,hm,hold);

signal state : state_type;

begin

pwr<='1';

bkpwr<='1';

rw<='0';

e <='1';

process(clk, reset)

begin

if reset = '0' then

state <= wt;

rs<='0';

data<= "00110000";

elsif rising_edge(clk) then

case state is

when wt =>

state<=wt1;

when wt1 =>

state<=wt2;

when wt2 =>

state<=funcset;

when funcset=>

rs<='0';

data<= X"30";

state<=displayoff;

when displayoff=>

rs<='0';

data<= X"08";

state<=displayon;

when displayon=>

rs<='0';

data<= X"0E";

state<=displayclr;

when displayclr=>

rs<='0';

data<= X"01";

state<=entry;

when entry=>

rs<='0';

data<= X"06";

state<=wrt;

when wrt=>

rs<='1';

data<= X"48";

state<=wrt1;

when wrt1=>

rs<='1';

data<= X"49";

state<=wrt2;

when wrt2=>

rs<='1';

data<= X"48";

state<=wrt3;

when wrt3=>

rs<='1';

data<= X"54";

state<=wrt4;

when wrt4=>

rs<='1';

data<= X"41";

state<=wrt5;

when wrt5=>

rs<='1';

data<= X"43";

state<=wrt6;

when wrt6=>

rs<='1';

data<= X"48";

state<=wrt7;

when wrt7=>

rs<='1';

data<= X"49";

state<=entry1;

when entry1=>

rs<='0';

data<= X"07";

state<=wrt8;

when wrt8=>

rs<='1';

data<= X"20";

state<=hm;

when hm=>

rs<='0';

data<= X"02";

state<=hold;

when hold=>

rs<='0';

state<=state;

end case;

end if;

end process;

end behv;

entity hitachi_top is port(

resetx,clkx : in std_logic;

rsx,rwx ,ex,pwrx,bkpwrx : out std_logic;

datax : out std_logic_vector(7 downto 0)

);

end hitachi_top;

architecture Behavioral of hitachi_top is

component hitachi port (

reset,clk : in std_logic;

rs,rw ,e,pwr,bkpwr : out std_logic;

data : out std_logic_vector(7 downto 0)

);

end component;

component div25 port (

clkf : in std_logic;

clk25 : out std_logic

);

end component;

signal clk: std_logic;

begin

l1: hitachi port map (reset=>resetx,clk=> clk, rs=>rsx, rw=>rwx,

e=>ex, data =>datax,bkpwr=>bkpwrx, pwr=>pwrx);

l2: div25 port map (clkf=>clkx, clk25=>clk);

end Behavioral;

entity div25 is

port( clkf : in std_logic;

clk25 : out std_logic

);

end;

architecture rtl of div25 is

signal count: integer range 0 to 125000;

begin

process(clkf)

begin

if (clkf'event and clkf = '1') then

if count<124999 then

count<=count+1;

else

count<= 0;

end if;

if count < 62500 then

clk25 <= '1';

else

clk25 <= '0';

end if;

end if;

end process;

end;