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Altera_Forum's avatar
Altera_Forum
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15 years ago

VHDL Counter

I am new to VHDL, and I am trying to create a counter that will count up from 0 to X when a signal called enable will be true. I get errors like Latches are generated for incomplete case or if ...
Altera_Forum's avatar
Altera_Forum
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15 years ago

I know I am posting in an Altera Website... I am using Xilinx ISE... It complains if it is not in the sensitivity list. Also, as I understand it, the reason why you put it in the sensitivity list is so that the "event" when any of the signals within the process(*) changes state, the process block will execute.

So I would think if the enable happens to change, as it is in my case of a random signal, I need to be able to start and stop my counter. If I don't put it there, there is a chance my counter will neither stop or start its counting process. So I don't completely agree with your statement, but I have been proven wrong other times.

I am not very experienced VHDL writer. I only do glue logic with CPLDS...