VHDL Counter

I figured out a work around I just created a simple counter. I created a separate unit which provide a reset signal so I can reset the counters. I also made sure the counter counts only when enable is true.

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Entry port 
entity Counter is
     generic(N: integer :=16);                   --Scale it to 20 bits counter
    port ( clk         : in  STD_LOGIC;
           enable        : in     STD_LOGIC;        --Enable this counter
              reset        : in  STD_LOGIC;
              max_ticks    : out STD_LOGIC;
              cnts_out     : out  STD_LOGIC_VECTOR (N-1 downto 0));
end Counter;
architecture Behavioral of Counter is
signal r_reg: std_logic_vector (N-1 downto 0) := (others =>'0');
BEGIN
PCntr: process(clk,reset,enable) 
    begin
        if(reset='1') then
            r_reg <= (others => '0');
        elsif(rising_edge(clk)) then
            if(enable='1') then
                r_reg <= r_reg + 1;
            else
                r_reg <=(others => '0');
            end if;
        end if;
end process PCntr;
    
--Output logic
max_ticks <= '1' when r_reg = (2**N-1) else '0';    --Overflow counter indicator     
cnts_out <= r_reg;
end Behavioral;