VHDL Counter

I suggest you try the code I posted, without the enable = '0' reset condition.

For the bit you dont understand, you have to remember that what you are trying to do is describe hardware, not write code. For what I posted, the enable_r signal will always be what enable was 1 clock cycle ago. This way you can check to see if enable has changed since the last clock cycle. The "if" statement I put in detects a falling edge on the enable signal. This is the only way to detect falling/rising edges in logic (clocks are a special case).

With the variable you added, you never actually set the value of X to anything other than 0, so r_reg will always be 1.