VHDL Counter

Guys,

I have modified the code you provided in an effort to get my counter to count up, and to reset it before it starts again based on the Enable signal = '1'. One thing I didn't mention is that the counter will not reach its rollover point, so I have to reset it some how before I reuse it.

I am not sure the changes are correct but all the stuff I added is in RED, and comments are in green Would this work?

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
 
entity Counter is
     generic(N: integer :=16);                   --Scale it to 20bits counter
    port ( clk         : in  STD_LOGIC;
           enable        : in     STD_LOGIC;        --Enable this counter
              reset        : in  STD_LOGIC;
              max_ticks    : out std_logic;
              cnts_out     : out  STD_LOGIC_VECTOR (N-1 downto 0));
end Counter;
 
 
architecture Behavioral of Counter is
 
  signal r_reg: unsigned(N-1 downto 0):= to_unsigned(0, N);  --use to_unsigned function so that it works with the generic N
  signal q_reg: unsigned(N-1 downto 0):= to_unsigned(0,N); 
 signal enable_r : std_logic;   --enable register
 
begin
 
  pCntr: process(clk,reset)   --no need for enable in here
  Variable X: integer range 0 to ((2**N)-1);    -- Will this work?
  begin
    if(reset = '1') then
      r_reg <= (others => '0');
    elsif rising_edge(clk) then          
      if enable = '1' then
        r_reg <= X + 1;     --Increment - this rolls over back to 0
      end if;
    end if;
 
-- I need to start counting from zero next time I come back into the counter
-- A signal controller is toggling the enable back High/low, but the r_reg
-- will hold the previous value unless it sees a reset coming in which I don't
-- available.  I am trying to clear out the r_reg so that after is sent
 
-- How does this change detect the edge? If I am not mistaken (bear with
-- me I am new to VHDL) it seems to me enable_r stores the state in the 
-- first rising edge, since everything executes sequentially, the second time
-- in the previous state will get over-written and the if() will not fire!  What
-- is the explanation of this code so I understand why this works?
 
     --Register enable so we can detect falling edge
      enable_r <= enable;
 
 
-- This code may generate the same warning since it does not have
-- the else condition on it, unless I add this...
 
--    if ((enable_r = '1') and (enable = '0')) then  --falling edge of enable
 
if(enable = '0') then
  cnts_out <= std_logic_vector (r_reg);  --Changed to this since unsigned is different type than cnts_out right!
  X := 0;  --Reset the counter
else
  cnts_out <= std_logic_vector(q_reg)   --Does this work?
end if;
 
  end process;
 
  --Set an overflow Flag in due case we reach the maximum counts
  max_ticks <= '1' when r_reg = (2**N-1) else '0';    --Overflow counter indicator    
end Behavioral;