VHDL Counter

Logically red:your code will work in a simulator, but wont work on an FPGA because you're trying to use the enable signal as a clock, which is not allowed.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Counter is
     generic(N: integer :=16);                   --Scale it to 20bits counter
    port ( clk         : in  STD_LOGIC;
           enable        : in     STD_LOGIC;        --Enable this counter
              reset        : in  STD_LOGIC;
              max_ticks    : out std_logic;
              cnts_out     : out  STD_LOGIC_VECTOR (N-1 downto 0));
end Counter;
architecture Behavioral of Counter is
  signal r_reg: unsigned(N-1 downto 0):= to_unsigned(0, N);  --use to_unsigned function so that it works with the generic N
  signal enable_r : std_logic;   --enable register
begin
    
  pCntr: process(clk,reset)   --no need for enable in here
  begin
    if(reset = '1') then
      r_reg <= (others => '0');
      
    elsif rising_edge(clk) then          
      if enable = '1' then
        r_reg <= r_reg + 1;     --Increment - this rolls over back to 0
        
      end if;
        
      --Register enable so we can detect falling edge
      enable_r <= enable;
      
      if enable_r = '1' and enable = '0' then  --falling edge of enable
        cnts_out   <= r_reg;
      end if;
    end if;
  end process;
  
  --Set an overflow Flag in due case we reach the maximum counts
  max_ticks <= '1' when r_reg = (2**N-1) else '0';    --Overflow counter indicator    
end Behavioral;