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Altera_Forum
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15 years ago

VHDL constant type synthesis

The constant type here is two-dimension data array constant which is correct when simulating in Modelsim, but is false when mearsured using oscillograph because I can't reach the inner unit of the co...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Like the sentence constant RAM:=("....","...",...), I need to reach any index I want when conditions meet. I realize it logically which is correct when simulating, but it went wrong when debug on board using oscillograph. The problem is I can't reach the index I want , or I can't see it in oscillograph