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Altera_Forum
Honored Contributor
16 years agoVHDL constant type synthesis
The constant type here is two-dimension data array constant which is correct when simulating in Modelsim, but is false when mearsured using oscillograph because I can't reach the inner unit of the co...
Altera_Forum
Honored Contributor
16 years agoI'd suggest to explain your problem a bit more because I didn't understand anything.