Altera_Forum
Honored Contributor
13 years agoVHDL Code-Multiplication
I am new to this site. I have to work on a project which needs vhdl coding and I am new to it too.
i just need to multiply two elements . so i do that by entering a*b. but i get this error " found 0 defntiions of operator "*" " .i have included these libraries use IEEE.STD_LOGIC_1164.all; use ieee.numeric_std.all; use ieee.std_logic_arith.all; i have tried giving it this way.. result <= std_logic_vector(a*b) seeing one of the forums. then I get the following error. near std_logic_vector " type conversion expression type cannot be determined uniquely" a and b can be complex numbers Please help me. How could just multiplication of two elements have so many complications in VHDL ? :(