vhdl code for tic tac game

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_arith.all;

entity tic_tac is

port(S1: in std_logic;

S2: in std_logic;

S3: in std_logic;

S4: in std_logic;

S5: in std_logic;

S6: in std_logic;

S7: in std_logic;

S8: in std_logic;

S9: in std_logic; -- nine different switch --

clk : in std_logic;

rst : in std_logic;

G1: out std_logic;

G2: out std_logic;

G3: out std_logic;

G4: out std_logic;

G5: out std_logic;

G6: out std_logic;

G7: out std_logic;

G8: out std_logic;

G9: out std_logic; -- output diode

D1,D2 : out std_logic);-- WINNER indicator led

end tic_tac;

architecture rtl of tic_tac is

signal sig,count,l1p1,l2p1,l3p1,l4p1,l5p1,l6p1,l7p1,l8p1,l9p1,l1p2,l2p2,l3p2,l4p2,l5p2,l6p2,l7p2,l8p2,l9p2,

player2 : std_logic;

begin

sig <= S1 or S2 or S3 or S4 or S5 or S6 or S7 or S8 or S9;

g1<=l1p1 or (l1p2 and clk) ;

g2<=l2p1 or (l2p2 and clk) ;

g3<=l3p1 or (l3p2 and clk) ;

g4<=l4p1 or (l4p2 and clk) ;

g5<=l5p1 or (l5p2 and clk) ;

g6<=l6p1 or (l6p2 and clk) ;

g7<=l7p1 or (l7p2 and clk) ;

g8<=l8p1 or (l8p2 and clk) ;

g9<=l9p1 or (l9p2 and clk) ;

process(sig,rst)

begin

if (rst='1') then

count<= '0';

elsif rising_edge(sig) then

count <= not count;

end if;

end process;

process(count,player2)

begin

------------------------------------------

---------two player were selected---------

------------------------------------------

if count ='0' then

player2<='1';

else

player2 <='0';

end if;

end process;

process(rst,S1,S2,s3,s4,s5,s6,s7,s8,s9)

begin

if rst = '1' then

l1p1<= '0';

l2p1<= '0';

l3p1<= '0';

l4p1<= '0';

l5p1<= '0';

l6p1<= '0';

l7p1<= '0';

l8p1<= '0';

l9p1<= '0';

l1p2<= '0';

l2p2<= '0';

l3p2<= '0';

l4p2<= '0';

l5p2<= '0';

l6p2<= '0';

l7p2<= '0';

l8p2<= '0';

l9p2<= '0';

elsif s1= '1' then

l1p2<= count;

l1p1<= not count;

elsif s2 ='1' then

l2p2<= count;

l2p1<= not count;

elsif s3 ='1' then

l3p2<= count;

l3p1<= not count;

elsif s4 ='1' then

l4p2<= count;

l4p1<= not count;

elsif s5 ='1' then

l5p2<= count;

l5p1<= not count;

elsif s6 ='1' then

l6p2<= count;

l6p1<= not count;

elsif s7 ='1' then

l7p2<= count;

l7p1<= not count;

elsif s8 ='1' then

l8p2<= count;

l8p1<= not count;

elsif s9 ='1' then

l9p2<= count;

l9p1<= not count;

end if;

end process;

d1<=(l1p1 and l2p1 and l3p1) or (l1p1 and l5p1 and l9p1) or (l1p1 and l4p1 and l7p1)

or(l4p1 and l5p1 and l6p1) or (l7p1 and l8p1 and l9p1) or (l7p1 and l5p1 and l3p1) or (l8p1 and l5p1 and l2p1)

or (l9p1 and l6p1 and l3p1);

d2<= (l1p2 and l2p2 and l3p2) or (l1p2 and l5p2 and l9p2) or (l1p2 and l4p2 and l7p2)

or(l4p2 and l5p2 and l6p2) or (l7p2 and l8p2 and l9p2) or (l7p2 and l5p2 and l3p2) or (l8p2 and l5p2 and l2p2)

or (l9p2 and l6p2 and l3p2);

end rtl;

this my code, and its working fine. i write code for testbench also it working but but i face lots of latches while load in FPGA board