vhdl-car park monitoring system

You are on track but your time clock does not look right to me.

first "count" must be constrained integer.

your clk input is 1 msec period hence 1000 periods means 1 second

let count run between 0 ~ 999

do not produce gated clk (clk = not clk).

run all counting on system clk

process(reset,midnight_sync,clk)
if reset or midnight_sync ....
elsif(rising_edge(clk))then
   if msec_count /= 999 then
        msec_count <= msec_count + 1;
   else 
        msec_count <= 0;
        if sec_count /= 59 then
           sec_count <= sec_count + 1;
        else
           sec_count <= 0;
           if min_count /= 59 then
              min_count <= min_count + 1;
           else
              min_count <= 0;
              if hr_count /= 23 then
                    hr_count <= hr_count + 1;
               else
                    hr_count <= 0;
               end if;
           end if;
       end if;
  enf if;
end if;